1. Field of the Invention
The present invention relates to liquid crystal display devices, and more particularly, to a liquid crystal display device for improving a picture quality.
2. Discussion of the Related Art
In keeping pace with developments of an information oriented society, demands for display devices has increased in various forms. Recently, to meet the demands, various flat display devices such as LCDs (Liquid Crystal Display Device), PDPs (Plasma Display Panel), ELDs (Electro Luminescent Display), VFDs (Vacuum Fluorescent Display), and so on have been studied, some of which are being used as display devices in various apparatuses.
Of the various display devices, the LCD has been used mostly for mobile display devices owing to advantages of good picture quality, lightweight, thin profile, and low power consumption. In addition to mobile display devices such as monitors for notebook computers, the LCD has been developed in various forms as monitors for televisions for receiving and displaying a broadcasting signal and as monitors for desktop computers.
For using the LCD as general display devices, key development of the LCD lies in further realizing high quality picture, such as high definition, high luminance, and large sized picture, while maintaining the features of lightweight, thin profile, and low power consumption.
An LCD is provided with a liquid crystal panel for displaying a picture, and a driving unit for applying a driving signal to the liquid crystal panel. The liquid crystal display panel is provided with first and second glass substrates bonded together with a space between the substrates, and a liquid crystal layer between the first and the second glass substrates.
Formed on the first glass substrate (or a TFT array substrate) are a plurality of gate lines arranged at regular intervals in one direction, a plurality of data lines arranged at regular intervals perpendicular to the gate lines, a plurality of pixel electrodes on every pixel region defined at every intersection between the gate lines and the data lines in a form of matrix, and a plurality of thin film transistors (TFT) to be switched in response to a signal on the gate line for transmission of a signal on the data line to each pixel electrode.
Formed on the second glass substrate (or a color filter substrate) are a black matrix layer for shielding a light incident on parts excluding the pixel regions, R, G, and B color filter layers for expressing colors, and a common electrode for displaying a picture.
A driving principle of a general liquid crystal display device lies on using optical anisotropy and polarizing properties of liquid crystals. Since the liquid crystal is thin and elongated, molecules of the liquid crystals tend to orient such that applying an electric field to the liquid crystals can control orientation of a molecular arrangement of the liquid crystals.
Therefore, if the orientation of the molecular arrangement of the liquid crystals is controlled, the molecular arrangement of the liquid crystals is controlled, and the light refracts in a direction of the desired orientation of the molecular arrangement of the liquid crystals, thereby enabling the display of the picture information.
Presently, the Active Matrix LCD, in which thin film transistors and pixel electrodes connected thereto are arranged in a matrix, has attracted the most interest due to its good resolution and motion picture implementing capability.
A related art liquid crystal display device will be described with reference to the attached drawings.
Referring to FIG. 1, the related art liquid crystal display panel is provided with a first substrate 1 and a second substrate 2 bonded together with a space between the substrates, and liquid crystals 3 between the first substrate 1 and the second substrate 2.
Arranged on the first substrate 1 are a plurality of gate lines 4 at regular intervals in one direction, and a plurality of data lines 5 at regular intervals perpendicular to the gate lines 4 to define pixel regions ‘P’, wherein a pixel electrode 6 is formed on each of pixel regions ‘P’. A plurality of thin film transistors ‘T’ are respectively formed at portions where the gate lines 4 and the data lines 5 intersect so as to be driven in response to a signal on the gate line 4 for transmission of a data signal from the data line 5 to each pixel electrode 6.
A black matrix layer 7 is formed on the second substrate 2 for shielding light incident on portions excluding the pixel regions ‘P’. R, G, and B color filter layers 8 for expressing colors and a common electrode 9 are also formed on the second substrate 2 for displaying a picture.
The thin film transistor ‘T’ is provided with a gate electrode projected from the gate line 4, a gate insulating film (not shown) is formed on an entire surface, an active layer (not shown) is formed on the gate insulating film over the gate electrode, a source electrode is projected from the data line 5, and a drain electrode is spaced a predetermined distance from the source electrode.
The pixel electrode 6 is in contact with the drain electrode for being turned on/off in response to a signal received as the thin film transistor ‘T’ is driven. The pixel electrode 6 is formed from a transparent conductive metal having a good light transmittivity such as ITO (Indium Tin Oxide).
FIG. 2 illustrates an enlarged view showing a wiring of a pixel region, a link region, and a pad region of a related art liquid crystal display device.
Referring to FIG. 2, the wiring of the related art liquid crystal display device is formed such that a space between adjacent lines becomes smaller as the wiring proceeds from the pixel region to the pad region via the link region. This is because a drive-IC (not shown) formed opposite to the pad region for receiving line signals from a system has a width relatively smaller than a width of the plurality of the gate lines or data lines connected to the drive-IC. The gate lines or the data lines in the pixel region 15a are extended to pad lines 15c via link lines 15b. 
A configuration at a center portion ‘C’ is different from a configuration at an edge portion E. That is, while the wiring at the center portion ‘C’ of the drive-IC runs on a straight line through the pixel region, the link region, and the pad region, the wiring at the edge portion ‘E’ of the drive-IC has different pitches between the wiring 15a at the pixel region and the wiring 15c at the pads, the pitch of the wiring at the link 15b between the pixel region and the pad region is reduced as the wiring goes from the pixel region toward the pad region.
FIG. 3 illustrates a plan view of a wiring of a related art liquid crystal display device, and FIG. 4 illustrates an enlarged view of wiring of a third Tape Carrier Package (TCP) in FIG. 3.
Referring to FIG. 3, the related art liquid crystal display device is provided with a liquid crystal panel 10 having first substrate 1 and a second substrate 2 opposite each other and a liquid crystal layer (not shown) between the first and second substrates 1 and 2. The liquid crystal display panel 10 has a pixel region (inside the dashed lines) defined at a center portion and a non-display portion (outside the dashed lines) defined on an outside of the pixel region. The non-display portion is provided with a pad region where gate drive-ICs 12 and data drive-ICs 14 are connected thereto with respective gate TCPs 11a˜11d, and data TCPs 13a˜13c and 23a˜23c, and a link region between the pixel region and the pad region where the link wiring passes.
The gate drive-ICs 12 and the data drive-ICs 14 are connected to the pad region with corresponding TCP film. In the drawing, the gate drive-ICs 12 are connected to the pad region of the liquid crystal panel 10 with first to fourth gate TCPs 11a, 11b, 11c, and 11d respectively, and the data drive-ICs 14 are connected to the pad region of the liquid crystal panel 10 with first to sixth data TCPs 13a, 13b, 13c, 23a, 23b, and 23c. 
If the liquid crystal display device is driven in a two port system, i.e. if the first to third data TCP 13a, 13b, and 13c and the fourth to sixth data TCP 23a, 23b, and 23c receive data voltage signals from ports of a system different from each other, there are surplus first dummy portion 20a and a second dummy portion 20b at ends of the ports which do not receive signals from the ports.
The total number of output pins of the data TCPs 13a, 13b, 13c, 23a, 23b, and 23c are not the same with a total number of the data lines 15a on the liquid crystal panel 10. Therefore, in the two port system, if the pins of the data TCP are connected to the data lines 15a starting from a left side of the first port in succession, there are pins at an end of the first port, i.e. an end of the third TCP 13c, which do not have corresponding data lines 15a of the liquid crystal panel 10 and are left as surplus. Similarly, there are surplus pins at an end of the sixth TCP 23c. Thus, there are dummy pins (or called channels) at the third and sixth data TCPs 13c and 23c and are called as TCP dummy portions 20a and 20b, respectively. There are two dummy portions 20a and 20b in the two port system.
If there are more than two ports in the liquid crystal panel 10, the number of dummy portions at ends of the ports will match the number of the ports typically.
Referring to FIG. 4, there are six dummy pins at an end of the third data TCP 13c of the end of the first portion, i.e. at the first dummy portion 20a. It is likely that there is a same number of dummy pins at the second dummy portion 20b. 
It is assumed that the liquid crystal display device of the related art is in an SXGA display, with a resolution of 1280×1024. Thus, there are 1280×3=3840 data lines in the pixel region.
If it is assumed that there are 642 pins in each data TCP, and data mapping (connection of the pins of the data TCP to the data lines) is started from the left side, though all pins (642 pins) of the first data TCP 13a and the second data TCP 13b are matched and connected to the data lines 15a, only 636 pins of the third data TCP 13c are matched and connected to the data lines 15a. This leaves right most 6 dummy pins in the third data TCP 13c unmatched and unconnected to the data lines of the pixel region as illustrated in FIG. 4.
That is, the first data TCP 13a has the first to 642nd data lines (#1˜#642) connected thereto, the second data TCP 13b has 643rd to 1284th data lines (#643˜#1284) connected thereto, and the third data TCP 13c has 1285th to 1920th data lines (#1285˜#1920) connected thereto.
Moreover, the fourth data TCP 23a has 1921st to 2562nd data lines (#1921˜#2562) connected thereto, the fifth data TCP 23b has 2563rd to 3204th data lines (#2563˜#3204) connected thereto, and the sixth data TCP 23c has 3205th to 3840th data lines (#3205˜#3840) connected thereto.
Thus, there are first and second dummy portions 20a and 20b each with 6 pins at right side ends of the third data TCP 13c and the sixth data TCP 23c, respectively.
It should be noted that the number of dummy pins can change according to the number of pins of the TCP. That is, the number of dummy pins is a difference of a number of the output pins of the data TCPs and a number of the data lines 15a. 
The first dummy portion 20a between the third data TCP 13c and the fourth data TCP 23a causes a link resistance difference between the first dummy portion 20a and the link wiring in the vicinity of the first dummy portion 20a. As a result, a dim block is formed in the vicinity of the first dummy portion 20a causing a difference of luminance from neighboring portions of the panel.
That is, the dummy pins of the TCP dummy portion have resistance differences from neighboring link wiring, which causes differences in the rising and falling of the data signal supplied from a source drive-IC. This in turn causes a charging performance difference of pixel regions leading to a formation of the dim block at an interface of the drive-ICs.